81011hkpc/60408mspc 20080522-s00003 no.a1227-1/8 http://onsemi.com semiconductor components industries, llc, 2013 august, 2013 lv51130t overview the lv51130t is a protection ic for 2-cell lithium-ion secondary batteries. features ? monitoring function for each cell: detects overcharge and over-discharge conditions and controls the charging and discharging operation of each cell. ? high detection voltage accuracy: over-charge detection accuracy 25mv over-discharge detection accuracy 100mv ? hysteresis cancel function: th e hysteresis of over-discharge detection voltage is cancelled by connection of a load after over charging has been detected. ? discharge current monitoring function: detects over-currents, load shorting, and excessively high voltage of a charger. ? low current consumption: normal operation mode typ. 6.0 a stand by mode max. 0.2 a ? 0v cell charging function: charging is enabled even when the cell voltage is 0v by giving a voltage between the v dd pin and v - pin. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit power supply voltage v dd -0.3 to +12 v input voltage charger minus voltage v - v dd -28 to v dd +0.3 v cout pin voltage vcout v dd -28 to v dd +0.3 v output voltage dout pin voltage vdout v ss -0.3 to v dd +0.3 v allowable power dissipation pd max independent ic 170 mw operating ambient temperature topr -30 to +85 c storage temperature tstg -40 to +125 c ordering number : ena1227a cmos ic 2-cell lithium-ion secondary battery protection ic stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lv51130t no.a1227-2/8 electrical characteristics at ta = 25 c, unless especially specified. ratings parameter symbol conditions min typ max unit operation input voltage vcell voltage between v dd and v ss 1.5 10 v 0v cell charging minimum operation voltage vmin voltage between v dd -v - under v dd -v ss =0 1.5 v 4.325 4.350 4.375 v over-charge detection voltage vd1 ta=0 to 45 c *1 4.315 4.350 4.385 v v - vd3 4.100 4.150 4.200 v over-charge release voltage vr1 v - > vd3 4.250 4.360 v over-charge detection delay time td1 v dd -vc=3.5v 4.5v, vc-v ss =3.5v 0.5 1.0 1.5 s over-charge release delay time tr1 v dd -vc=4.5v 3.5v, vc-v ss =3.5v 20.0 40.0 60.0 ms over-discharge detection voltage vd2 2.20 2.30 2.40 v over-discharge release hysteresis voltage vh2 10.0 20.0 40.0 mv over-discharge detection delay time td2 v dd -vc=3.5v 2.2v, vc-v ss =3.5v 50 100 150 ms over-discharge release delay time tr2 v dd -vc=2.2v 3.5v, vc-v ss =3.5v 0.5 1.0 1.5 ms over-current detection voltage vd3 v dd -vc=3.5v, vc-v ss =3.5v 0.28 0.30 0.32 v over-current release hysteresis voltage vh3 v dd -vc=3.5v, vc-v ss =3.5v 5.0 10.0 20.0 mv over-current detection delay time td3 v dd -vc=3.5v, vc-v ss =3.5v 10.0 20.0 30.0 ms over-current release delay time tr3 v dd -vc=3.5v, vc-v ss =3.5v 0.5 1.0 1.5 ms short circuit detection voltage vd4 v dd -vc=3.5v, vc-v ss =3.5v 1.0 1.3 1.6 v short circuit detection delay time td4 v dd -vc=3.5v, vc-v ss =3.5v 0.125 0.250 0.500 ms excessive charger detection voltage vd5 v dd -vc=3.5v, vc-v ss =3.5v voltage between v - and v ss -0.60 -0.45 -0.30 v excessive charge detection release hysteresis voltage vh5 v dd -vc=3.5v, vc-v ss =3.5v 25.0 50.0 100.0 mv stand-by release voltage vstb v dd -vc=2.0v, vc-v ss =2.0v voltage between v - and v ss v dd 0.4 v dd 0.5 v dd 0.6 v excessive charger detection delay time td5 v dd -vc=3.5v, vc-v ss =3.5v *2 0.5 1.5 3.0 ms excessive charger release delay time tr5 v dd -vc=3.5v, vc-v ss =3.5v 0.5 1.5 3.0 ms internal resistance (vm-v dd ) r dd after over-discharge is detected. 100 200 400 k internal resistance (vm-v ss ) r ss after over-current or short-circuit is detected. 15 30 60 k cout nch on voltage v o l1 i o l=50 a, v dd -vc=4.4v, vc-v ss =4.4v 0.5 v cout pch on voltage v o h1 i o l=50 a, v dd -vc=3.9v, vc-v ss =3.9v v dd -0.5 v dout nch on voltage v o l2 i o l=50 a, v dd -vc=2.2v, vc-v ss =2.2v 0.5 v dout pch on voltage v o h2 i o l=50 a, v dd -vc=3.9v, vc-v ss =3.9v v dd -0.5 v vc input current ivc v dd -vc=3.5v, vc-v ss =3.5v 0.0 1.0 a current consumption i dd v dd -vc=3.5v, vc-v ss =3.5v 6.0 13.0 a stand-by current istb v dd -vc=2.2v, vc-v ss =3.5v 0.2 a t-terminal input on voltage vtest v dd -vc=3.5v, vc-v ss =3.5v v dd 0.4 v dd 0.5 v dd 0.6 v *1 the ratings of the table above is a design targets and are not measured. *2 under over-discharge state, delay operatio n starts after release of over-discharge.
lv51130t no.a1227-3/8 package dimensions unit : mm (typ) 3245b pin assignment pin functions pin no. symbol description 1 v dd v dd pin 2 cout overcharge detection output pin 3 v - charger minus voltage input pin 4 v ss v ss pin 5 sense sense pin 6 vc intermediate between both cell voltage input pin 7 t pin to shorten detection time (?h?:shortening mode, ?l? or ?open?:normal mode) 8 dout overdischarge detection output pin pd max -- ta -30 -20 0 20 40 60 80 100 68 0 50 100 150 200 170 independent ic ambient temperature, ta -- c allowable power dissipation, pd max -- mw 1 v dd 2 cout 3 v - 4 v ss 8 7 6 5 dout t vc sense top view sanyo : msop8(150mil) 3.0 1.1max 3.0 0.5 4.9 12 8 0.25 0.65 (0.53) (0.85) 0.125 0.08
lv51130t no.a1227-4/8 block diagram 6 + - + - + - + - 4 5 + - 3 td1,tr1 td2,tr2 td3,tr3 + - + - 1 td5,tr5 td4 2 8 v ss v - sence v dd vc cout dout 7 t level shift delay control logic
lv51130t no.a1227-5/8 functional description over-charge detection if either of the cell voltage is equal to or more than the over-charge detection voltage, stop further charging by turning ?l? the cout pin and turning off external nch mos fet after the over-charge detection delay time. this delay time is set by the internal counter. the over-charge detection comparator ha s the hysteresis function. note that this hysteresis can be cancelled by connecting the load after detection of ov er-charge detection. and it becomes smal l hysteresis comparator has its own. once over-charge detection is made, over-current detection is not made to prevent incorrect operations. note that short-circuit can be detected. over-charge release if both cell voltages become equal to or less than the over-charge release voltage when vm voltage is equal to or less than vd3, or when vm voltage is more than vd3 with load connected, the cout pin returns to ?h? after the over- charge release delay time se t by the internal counter. when vm voltage is more than vd3 with load connected and either cell or both cell voltages are equal to or more than the over-charge release voltage, the cout pin does not return to ?h?. but the load current flows through the parasitic diode of external nch mos fet on cout, conseq uently each cell voltage becomes equal to or less than over-charge release voltage, the cout pin returns to ?h.? after the over-charge release delay time. however, excessive voltage charger is connected as men tioned below, cout pin does not return to ?h? because excessive charger detection starts after over-charge release operation. over-discharge detection when either cell voltage is equal to or less than over-discharge voltage, the ic stops further discharging by turning the dout pin ?l? and turning off external nch mos fet after the over-charge detection delay time. the ic goes into stand-by mode after detecting over-discharge and its consumption current is kept at about 0a. after over-discharge detection, the v - pin will be connected to v dd pin via internal resistor (typ 200k ? ). over-discharge release release from over-discharge is made by only connecting charger. if the v - pin voltage becomes equal to or lower than the stand-by release voltage by connecting charger after detecting over-discharge, the ic is released from the stand-by state to start cell voltage monitoring. while both cell voltages are equal to or less than over-discharge voltages, charging will be made through the parasitic diode of external nch fet on dout pin. if both cell voltages become equal to or more than the over-discharge detection voltage by charging, the dout pin returns to ?h? after the over-discharge release delay time set by the internal counter. over-current detection when excessive current flows through the battery, the v - pin voltage rises by the on resister of external mos fet and becomes equal to or more than the over-current detection voltage, the dout pin turns to ?l? after the over-current detection delay time and the external nch mos fet is turn ed off to prevent excessive current in the circuit. the detection delay time is set by the inte rnal counter. after detection, the v - pin will be connected to v ss via internal resistor (typ. 30k ? ). it will not go into stand-by mode after detec ting over-current. short circuit detection if greater discharging current flow s through the battery and the v - pin voltage becomes equal to or more than the short-circuit detection voltage, it will go into short-circuit de tection state after the short circuit delay time shorter than the over-current detection delay time. wh en short-circuit is detected, just like the time of over-current detection, the dout pin turns to ?l? and external nch mos fet is turned off to prevent high current in the circuit. the v - pin will be connected to v ss after detection via internal resistor (typ. 30k ? ). it will not go into stand-by mode after detecting short circuit. over-current/short-detection release after detecting over-current or short ci rcuit, the internal resistor (typ. 30k ? ) between v - pin and v ss pin becomes effective. if the load resistor is removed, the v - pin voltage will be pulled down to the v ss level. thereafter, the ic will be released from the over-current/short-circuit detection state when the v - pin voltage becomes equal to or less than the over-current detection voltage, and the dout pin retu rns to ?h? after over-current release delay time set by the internal counter.
lv51130t no.a1227-6/8 excessive charger detection/release if the voltage between v - pin and v ss pin becomes equal to or less than the excessive charger detection voltage by connecting a charger, no charging can be made by turning the cout pin ?l? after delay time and turning off the external nch mos fet. if that voltage returns to equal to or more than the excessive charger detection voltage during detection delay time, the excessive charger detection will be stopped. if the voltage between v - pin and v ss pin becomes equal to or more than the excessive charger detection voltage after excessive charger detection, the cout returns to ?h? after delay time. the detection/return delay time is set internally. if dout pin is ?l?, charging will be made through the parasitic diode of external nch fet on dout pin. in that case, the voltage between v - pin and v ss pin is nearly -vf which is less than the excessive-charger detection voltage, therefore no excessive charger detection will be made during over-discharge, over-current and short-circuit detection. furthermore, if excessive voltage char ger is connected to the over-discharge d battery, no excessive charger detection is made while the dout pin is ?l?. but the battery is continued charging through the parasitic diode. if the battery voltage rises to the over-discharge detection voltage and the voltage between v - pin and v ss pin remains equal to or less than the excessive charger detection voltage, the dela y operation will be started after dout pin turns to ?h.? 0v cell charging operation if voltage between v dd and v becomes equal to or more than the 0v cell charging lowest operation voltage when the cell voltage is 0v, the cout pin turns to ?h? and charging is enabled. shorten the test time by turning t pin to the v dd , the delay times set by the internal counter can be cut. if t pin is ?open?, ?l? the delay times are normal. delay time not set by the counter just like as short circuit detection delay cannot be controlled by this pin. in some circuit-board layout, an excessive current at the load short might cause this ic be in miss operation like as in standby mode due to v ss line impedance. therefore we recommend that the t pin is connected to the v ss pin. operation in case of detection overlap overlap state operation in case of detection overlap state after detection during over-charge detection over-discharge detection is made over-charge detection is preferred. if over- discharge state continues even after over- charge detection, over-discharge detection is resumed. when over-charge state is made first, v - is released. when over-discharge is detected after over-charge state is made, the ic does not go into the stand-by mode. note that v - is connected to v dd via 200k ? . over-current detection is made (*1) both detections can be made in parallel. over-charge detection continues even when the over-current state is made first. if the over- charge state is made first, over-current detection is interrupted. (*2) when over-current state is made first, v - is connected to v ss via 30k ? . when over-charge state is made first, v - is released. during over-discharge detection over-charge detection is made over-discharge detection is interrupted and over-charge detection is preferred. when over- discharge state continues even after over- charge state is made, over-discharge detection is resumed. the ic does not go into the stand-by mode when over-discharge state is made after over- charge detection. note that v - is connected to v dd via 200k ? . over-current detection is made (*3) both detections can be made in parallel. over-discharge detection continues even when the over-current state is made first. but over- current detection is interrupted when the over- discharge state is made first. (*4) if over-current st ate is made first, v - will be connected to v ss via 30k ? . if over-discharge detection is made next, v - will be disconnected from v ss and connected to v dd via 200k ? to get into stand-by mode. if over-discharge state is made first, v - will be connected to v dd via 200k ? to get into standby state. over-charge detection is made (*1) (*2) during over-current detection over-discharge detection is made (*3) (*4) (note) short-circuit detection can be made independently. excessive charger detection cannot be made during over -discharge, over-current and short-circuit detection. and its delay time starts after the dout pin returns to ?h?.
lv51130t no.a1227-7/8 timing chart [cout output system] [dout output system] v dd v - vd1 vr1 vd2 vd3 vd4 v dd v ss v ss v dd dout td2 tr2 td3 tr3 td4 tr3 over-discharge detection state over-current detection state short-circuit detection state charger connection load connection v dd v - cout vd1 vr1 vd2 vd3 vd4 v dd v ss v - v dd td1 tr1 td1 tr1 vd5 td5 over-charger connection tr5 over-charge detection state over-charge detection state over-charger detection state hysteresis cancellation by load connection discharging via fetparasite di over-current occurrence to standby charging via fetparasite di v - v dd cout vd5 load short-circuit occurrence td2 td5 tr2 over-charger detection upon charging over-discharged battery is activated after return from over-charge. charger connection over-charger connection discharging via fetparasite di charging recovery depends on charger voltage when connecting charger. charger connection charger connection load connection load connection load connection load connection load connection load connection to standby
lv51130t ps no.a1227-8/8 application circuit example v dd cout v - v ss dout vc sense lv51130t + ? r1 r2 c1 c2 r4 r3 v ss c3 t components recommended value max unit r1, r2 100 500 r3 2k 4k r4 100 1k c1, c2, c3 0.1 1 f * these numbers don't mean to guara ntee the characteristic of the ic. * in addition to the components in the upper diagram, it is necessary to insert a capacitor with enough capacity between v dd and v ss of the ic as near as possible to stab ilize the power supply voltage to the ic. * it is advisable to connect the t pin with the v ss pin. there is no problem even if the t pin is left open. on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.
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